Date | May 2021 | Marks available | 2 | Reference code | 21M.1.SL.TZ0.3 |
Level | SL | Paper | 1 | Time zone | no time zone |
Command term | Draw | Question number | 3 | Adapted from | N/A |
Question
Draw the logic circuit represented by the following truth table.
Markscheme
Award [2 max]
Note: There could be many answers that are correct.
Example 1
Correct inputs and XOR gate;
NOT gate, correct final output and link from XOR gate;
Example 2
Award [2] max.
2 marks, 1 mark for each correct input in OR gate
Note: in this example the two inputs in OR gate are (NOT A AND NOT B )and (A AND B).
1 mark for drawing any 3 gates (complete with inputs and outputs)
Examiners report
A wide range of correct logic circuits were seen in answer to this question, including logic gates from the syllabus – the XOR and NOT gates, as well as above level responses, including the XNOR gate. Some candidates incorrectly used regular OR or NOR gates in their solutions.